Andrew's "ongoing work" record for the P2011 clock model. Many different versions, with annotations made during SBSI development in 2011-2013 - see version records.
PLM_67v3 model, with TWO stepfunctions. Simulates fine but as of 21 March 2013 did not optimise.
Step2 is usually off because amplitude=0, but can produce LD-DD transition at 262h. To do so, initiate with amplitudeStep1=0 and amplitudeStep2=1.
NB the step1 will still go to LL at 314h, so need to stop DD costing before then.
Originally submitted to PLaSMo on 2012-05-31 22:18:27
Created: 10th Jan 2019 at 17:40
Last updated: 22nd Jan 2019 at 18:19